Digi NS9750 Manuel d'utilisateur

NS9750 DatasheetThe NetSilicon® NS9750 is a single chip 0.13µm CMOS network-attached processor. The CPU is the ARM926EJ-S core with MMU, DSP extension

System configuration6       NS9750 Datasheet v3 There are 32 additional GPIO pins that are used to create a general purpose, user-defined ID r

System bootwww.netsilicon.com       7System bootThere are two ways to boot the NS9750 system (see Figure 2, "Two methods of booting NS9750

Reset8       NS9750 Datasheet v3 ResetMaster reset using an external reset pin resets NS9750. Only the AHB bus error status registers retain t

Resetwww.netsilicon.com       9Figure 3: Sample reset circuitYou can use one of four software resets to reset NS9750. Select the reset by setti

System Clock10       NS9750 Datasheet v3 System ClockThe system clock is provided to NS9750 by either a crystal or an external oscillator; Tab

USB clockwww.netsilicon.com       11The system clock provides clocks for CPU, AHB system bus, peripheral BBus, PCI/CardBus, LCD, timers, memory

NS9750 pinout and signal descriptions12       NS9750 Datasheet v3 NS9750 pinout and signal descriptionsEach pinout table applies to a specific

System Memory interfacewww.netsilicon.com       13C15 addr[12] 8 O Address bus signalB15 addr[13] 8 O Address bus signalA15 addr[14] 8 O Addres

System Memory interface14       NS9750 Datasheet v3 E25 data[8] 8 I/O Data bus signalD26 data[9] 8 I/O Data bus signalF23 data[10] 8 I/O Data

System Memory interface signalswww.netsilicon.com       15System Memory interface signalsTable 5 describes the System Memory interface signals

ii       NS9750 Data Sheet v3external bus expansion module. It includes a versatile embedded LCD controller supporting up to 16M color TFT

Ethernet interface16       NS9750 Datasheet v3 Ethernet interfaceclk_in[3:0] I Feedback clocks. Used for SDRAM devices.byte_lane_sel_n[3:0] O

Clock generation/system pinswww.netsilicon.com       17Clock generation/system pinsU2 rxd[2] N/C I Receive data bit 2 Pull low external to NS97

PCI interface18       NS9750 Datasheet v3 PCI interfaceThe PCI interface can be set to PCI host or PCI device (slave) using the boot_strap[1]

PCI interfacewww.netsilicon.com       19P26 ad[15] N/A I/O PCI time-multiplexed address/data busU24 ad[16] N/A I/O PCI time-multiplexed address

PCI/CardBus signals20       NS9750 Datasheet v3 PCI/CardBus signalsMost of the CardBus signals are the same as the PCI signals. Other CardBus

GPIO MUXwww.netsilicon.com       21GPIO MUXNote: The BBus utility contains the control pins for each GPIO MUX bit. Each pin can be selected ind

GPIO MUX22       NS9750 Datasheet v3 AE18 gpio[1] U 2 I/O 00 Ser port A RxData / Ser port A RxData /SPI port A din01 DMA ch 0 req (duplicate)0

GPIO MUXwww.netsilicon.com       23AF15 gpio[10] U 2 I/O 00 Ser port B RTS01 Reserved02 Reserved03: GPIO 10AD14 gpio[11] U 2 I/O 00 Ser port B

GPIO MUX24       NS9750 Datasheet v3 AD12 gpio[19] U 4 I/O 00 Ethernet CAM req01 LCD line-horz sync02 DMA ch 1 ack03 GPIO 19AC12 gpio[20] U 8

GPIO MUXwww.netsilicon.com       25AE9 gpio[28] U 4 I/O 00 Ext IRQ 1 (duplicate)01 LCD data bit 402 LCD data bit 8 (duplicate)03 GPIO 28AF8 gpi

ContentsNS9750 Features ... 1System-level interf

GPIO MUX26       NS9750 Datasheet v3 AE5 gpio[38] U 4 I/O 00 Reserved01 1284 Data 7 (bidirectional)02 LCD data bit 1403 GPIO 38AF4 gpio[39] U

LCD module signalswww.netsilicon.com       27LCD module signalsThe LCD module signals are multiplexed with GPIO pins. They include six control

LCD module signals28       NS9750 Datasheet v3 Table 12 shows which CLD[23:0] pins provide the pixel data to the STN panel for each mode of op

LCD module signalswww.netsilicon.com       29Table 13 shows which CLD[23:0] pins provide the pixel data to the TFT panel for each of the multip

I2C interface30       NS9750 Datasheet v3 I2C interfaceUSB InterfaceNotes: If not using the USB interface, these pins should be pulled down t

JTAG interface for ARM core/boundary scanwww.netsilicon.com       31JTAG interface for ARM core/boundary scanNote: trst_n must be pulsed low to

Power ground32       NS9750 Datasheet v3 Power groundM2 Tie to ground directlyM1 Tie to ground directlyN1 Tie to ground directlyN2 Tie to grou

Address and register mapswww.netsilicon.com       33Address and register mapsSystem address mapThe system memory address is divided to allow ac

System Control registers34       NS9750 Datasheet v3 System Control registersBase address Peripheral0x9000 0000 BBus DMA controller0x9010 0000

System Control registerswww.netsilicon.com       35A090 0048 Timer 1 Reload Count registerA090 004C Timer 2 Reload Count registerA090 0050 Time

iv       NS9750 Datasheet v3Inputs...

System Control registers36       NS9750 Datasheet v3 A090 00C8 Interrupt Vector Address Register Level 1A090 00CC Interrupt Vector Address Reg

System Control registerswww.netsilicon.com       37A090 0148 Int Config 4 Int Config 5 Int Config 6 Int Config 7A090 014C Int Config 8 Int Conf

Memory Controller registers38       NS9750 Datasheet v3 Memory Controller registersA090 01C8 Timer 14 Control registerA090 01CC Timer 15 Contr

Memory Controller registerswww.netsilicon.com       39A070 003C MPMCDynamictAPR Dynamic Memory Last Data Out to Active Time (tAPR)A070 0040 MPM

Memory Controller registers40       NS9750 Datasheet v3 A070 0234 MPMCStaticWaitWr1 Static Memory Write DelayA070 0238 MPMCStaticWaitTurn1 Sta

Ethernet Control and Status registerswww.netsilicon.com       41Ethernet Control and Status registersAddress Register DescriptionA060 0000 EGCR

PCI Configuration registers42       NS9750 Datasheet v3 PCI Configuration registersTwo registers are used to perform PCI configuration cycles,

PCI Arbiter Configuration registerswww.netsilicon.com       43PCI Arbiter Configuration registersRegister number 31:24 23:16 15:08 07:000x00 De

BBus Bridge Control and Status registers44       NS9750 Datasheet v3 BBus Bridge Control and Status registersA030 002C PINTR PCI Bridge Interr

BBus DMA Control and Status registerswww.netsilicon.com       45BBus DMA Control and Status registersAddress — DMA1Address — DMA2Description900

NS9750 Featureswww.netsilicon.com       1NS9750 Features32-bit ARM926EJ-S RISC processor 125 to 200 MHz 5-stage pipeline with interlocking H

BBus DMA Control and Status registers46       NS9750 Datasheet v3 9000 00309011 0030DMA Channel 2 Control register9000 00509011 0050DMA Channe

BBus Utility Control and Status registerswww.netsilicon.com       47BBus Utility Control and Status registers9000 00749011 0074DMA Channel 4 St

I2C48       NS9750 Datasheet v3 I2CLCD Controller registers9060 0018 GPIO Configuration Register #39060 001C GPIO Configuration Register #4906

Serial Controller registerswww.netsilicon.com       49Serial Controller registersThe Serial Controller module contains four serial ports, refer

Serial Controller registers50       NS9750 Datasheet v3 9020 0034 Channel 1 Flow Control9020 0038 Channel 1 Transmit Override9020 0040 Channel

IEEE 1284 Peripheral Controller registerswww.netsilicon.com       51IEEE 1284 Peripheral Controller registers9030 0040 Channel 4 Control Regist

IEEE 1284 Peripheral Controller registers52       NS9750 Datasheet v3 9040 0100 – 9040 017C CSRs (8-bit wide)9040 0100 PD Printer Data Pins re

USB Configuration registerswww.netsilicon.com       53USB Configuration registersNote: USB device DMA registers are listed in "BBus DMA Co

USB Configuration registers54       NS9750 Datasheet v3 9010 200C Physical Endpoint Descriptor #39010 2010 Physical Endpoint Descriptor #49010

USB Configuration registerswww.netsilicon.com       559010 30A4 FIFO Packet Control #109010 30A8 FIFO Packet Control #119010 30AC FIFO Packet C

NS9750 Features2       NS9750 Datasheet v3  Internal or external clock support, digital PLL for Rx clock extraction 4 receive-side data matc

Electrical characteristics56       NS9750 Datasheet v3 Electrical characteristicsThe NS9750 operates at a 1.5V core, with 3.3V I/O ring voltag

Maximum power dissipationwww.netsilicon.com       57Maximum power dissipationTable 35 shows the maximum power dissipation, including sleep mode

DC electrical characteristics58       NS9750 Datasheet v3 DC electrical characteristicsDC electrical characteristics specify the worst-case DC

Power sequencingwww.netsilicon.com       59Power sequencingAll of the 3.3V and 1.5V power should be applied and removed within 100 milliseconds

AC Characteristics60       NS9750 Datasheet v3 AC CharacteristicsThis section provides the AC characteristics, or timing specifications, integ

Memory controller timing diagramswww.netsilicon.com       61sdram_read_cmd_dlyFigure 6: SDRAM read: command out delayed, cas latency=3Notes:1 T

Memory controller timing diagrams62       NS9750 Datasheet v3 sdram_read_clk_dlyFigure 7: SDRAM read: clock out delayed, cas latency=3Notes:1

Memory controller timing diagramswww.netsilicon.com       63sdram_write_cmd_dlyFigure 8: SDRAM write: command out delayed, cas latency=3Notes:1

Memory controller timing diagrams64       NS9750 Datasheet v3 sdram_write_clk_dlyFigure 9: SDRAM write: clock out delayed, cas latency=3Notes:

Memory controller timing diagramswww.netsilicon.com       65Table 37 describes the values shown in the memory controller SRAM timing diagrams (

System-level interfaceswww.netsilicon.com       3System-level interfacesFigure 1 shows the NS9750 system-level hardware interfaces, which are f

Memory controller timing diagrams66       NS9750 Datasheet v3 sram_writeFigure 11: SRAM write timing parametersNotes:1 st_cs_n assert to we_n

Reset timing diagramwww.netsilicon.com       67Reset timing diagramTable 38 describes the values shown in the Reset timing diagram. Figure 12 s

LCD controller timing diagrams68       NS9750 Datasheet v3 LCD controller timing diagramsTable 39 describes the values shown in the LCD contro

LCD controller timing diagramswww.netsilicon.com       694 The PPL (pixels per line) field in the LCDTiming0 register must also be programmed c

LCD controller timing diagrams70       NS9750 Datasheet v3 lcd_tft_syncFigure 16: Vertical timing parameters for TFT displaysT7T8T7 T9T8T10T11

Power supplywww.netsilicon.com       71Power supplyPlease contact the factory for proposed schematics.

Packaging72       NS9750 Datasheet v3 PackagingThe NS9750 dimensions and pinout are shown in the next two diagrams.Figure 17: NS9750 top view3

Packagingwww.netsilicon.com       73Figure 18: NS9750 bottom and side viewABCDEFGHJKLMNPRTUVWYAAABACADAEAF234 561 7 8 9 10 11 12 13 14 15 16 17

Part ordering information74       NS9750 Datasheet v3 Part ordering informationTBD

System-level interfaces4       NS9750 Datasheet v3 — Sixteen 16-bit or 32-bit programmable timers or counters— Two control signals to support

NetSilicon, Inc.411 Waverly Oaks RoadWaltham MA 02452781 647-1234 or 800 243-2333P/N: 91001206 ARelease date: July 2003© 2002-2003 NetSilicon, Inc.Pr

System configurationwww.netsilicon.com       5System configurationThe PLL and other system settings can be configured at powerup before the CPU