Digi NS9215 manuels

Digi NS9215 Manuel d'utilisateur (517 pages)

marque: Digi | Catégorie: Matériel | Taille: 2.21 MB |

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Table des matières

Hardware Reference

1

Contents

5

Hardware Reference NS9215

10

Pinout (265)

27

Memory bus interface

28

Ethernet interface MAC

30

PINOUT (265)

32

System clock

44

JTAG Test

48

POR and battery-backed logic

50

Power and ground

52

I/O Control Module

53

I/O CONTROL MODULE

54

GPIO3 GPIO2

56

GPI O19 GPI O18

58

GPIO39 GPIO38

60

GPI O55 GPI O54

62

GPI O71 GPI O70

64

GPIO83 GPIO82

66

GPIO103 GPI O102

68

GPIO Control registers

70

GPIO Control

72

Register #2

72

Address: A090_2074

72

GPIO Status registers

74

Working with the CPU

81

Instruction sets

82

84 Hardware Reference NS9215

84

MRC p15,0,Rd,c0,c0,{0, 3-7}

86

MRC p15,0,Rd,c0,c0,1

86

R1: Control register

88

SHOULD BE ONE

90

R4 register

92

R5: Fault Status registers

92

R7:Cache Operations register

94

MCR p15, 0, Rd, c7, c10, 4

96

MCR p15, 0, Rd, c7, c0, 4

96

R9: Cache Lockdown register

98

WORKING WITH THE CPU

100

. . . .

101

R11 and R12 registers

102

R13:Process ID register

102

R14 register

104

R15: Test and debug register

104

Jazelle(Java)

104

MemoryManagement Unit (MMU)

106

31 014 13

108

Translation table base

108

120 Hardware Reference NS9215

120

Fault checking sequence

122

TLB structure

126

Caches and write buffer

128

Cache MVA and Set/Way formats

130

System Control Module

137

System bus arbiter

138

SYSTEM CONTROL MODULE

140

Programmable timers

142

Basic PWM function

144

Clockwise

146

Interrupt controller

148

Bootstrap initialization

152

Register address

154

AHB Error Detect Status 2

160

Timer Master Control register

162

Timer 0–4 Control registers

164

Timer 5 Control register

166

Timer 6–9 Control registers

168

Timer 6–9 High registers

170

13121110987654321015 14

174

Cap Read

174

Read 15:0

174

ISADDR register

176

Interrupt Status Raw

178

Clock Configuration register

180

Module Reset register

182

Address: A090 0184

184

Register

184

PLL Configuration register

186

Register bit

188

AHB Bus Activity Status

190

Mask registers

190

194 Hardware Reference NS9215

194

196 Hardware Reference NS9215

196

Gen ID register

198

Standby

200

RTC Module Control register

202

Memory Controller

203

Low-power operation

204

Memory map

206

0x00000000 in memory

206

0x00000000

206

0x00000000 after

206

MEMORY CONTROLLER

208

Static memory read control

210

Asynchronous page mode read

214

Static memory write control

216

Address connectivity

222

Registers

230

Control register

232

Status register

234

Configuration register

234

Address: A070 0024

236

238 Hardware Reference NS9215

238

240 Hardware Reference NS9215

240

242 Hardware Reference NS9215

242

244 Hardware Reference NS9215

244

Time register

246

248 Hardware Reference NS9215

248

250 Hardware Reference NS9215

250

254 Hardware Reference NS9215

254

256 Hardware Reference NS9215

256

258 Hardware Reference NS9215

258

Ethernet Communication Module

261

Ethernet MAC

262

Station address logic (SAL)

264

Ethernet front-end module

266

ETHERNET COMMUNICATION MODULE

268

31 151630 29 28

270

Clock synchronization

276

284 Hardware Reference NS9215

284

TX_WR logic stops

286

MAC Configuration Register #1

288

0x55 and is error-free

290

Address: A060 040C

292

Maximum Frame register

294

Clocks field

296

Address: A060 0424

296

298 Hardware Reference NS9215

298

Station Address registers

300

RegisterHash Tables

302

312 Hardware Reference NS9215

312

314 Hardware Reference NS9215

314

316 Hardware Reference NS9215

316

Address: A060 0A18

320

Address: A060 0A24

322

324 Hardware Reference NS9215

324

RX Free Buffer register

326

TX Buffer Descriptor RAM

332

Sample hash table code

334

External DMA

339

DMA buffer descriptor

340

Peripheral DMA read access

342

EXTERNAL DMA

344

Control and Status registers

346

DMA Buffer Descriptor Pointer

346

Address: A080_0008, A080_0018

350

Not used

352

Not used SEL

352

Block diagram

356

CCM mode

362

I/O Hub Module

363

DMA controller

364

I/O HUB MODULE

366

W=1 , I=0, L=0, F=0

368

UART C register

370

UART D register

370

[Module] DMA TX Control

380

Serial Control Module: UART

385

Normal mode operation

386

Hardware-based flow control

388

Forced character transmission

388

SERIAL CONTROL MODULE: UART

390

N = ((FCLK * gap+period) - 1)

398

Transmit Byte Count

404

UART Baud Rate Divisor LSB

406

UART Baud Rate Divisor MSB

406

UART Modem Status register

412

Serial Control Module: HDLC

415

Clocking

416

SERIAL CONTROL MODULE: HDLC

418

Interrupt Enable register

424

HDLC Data register 3

428

HDLC Clock Divider Low

430

Serial Control Module: SPI

433

SPI controller

434

SPI clock generation

436

SERIAL CONTROL MODULE: SPI

438

Clock Generation register

440

Interrupt Status register

442

SPI timing characteristics

446

I2C Master/Slave Interface

447

C external addresses

448

C registers

450

Master Address register

452

Software driver

456

Slave module

458

(normal mode, 16

458

Real Time Clock Module

459

RTC General Control register

460

Time Alarm register

464

Event Flags register

466

REAL TIME CLOCK MODULE

470

General Status register

472

Analog-to-Digital Converter

473

(ADC) Module

473

ADC DMA procedure

474

Memory Timing

484

SDRAM burst

486

SDRAM refresh

492

Values in SRAM

494

Slow peripheral

502

C timing diagram

504

B/A/C/D Control Register A

508

JTAG timing

510

Clock timing

512

Packaging

513

Processor Dimensions

514

Change log

517

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